Power/performance optimization through temperature/voltage control

ABSTRACT

A method of optimizing power and timing for an integrated circuit (IC) chip, identifies a plurality of valid temperature and voltage combinations that allow integrated circuit chips produced according to the integrated circuit chip design to operate within average power consumption goals and timing delay goals. Such a method selects temperature cut points from the valid temperature and voltage combinations for each of the integrated circuit chips, calculates a power consumption amount of each of the temperature cut points, and adjusts the temperature cut points based on the power consumption amount until the temperature cut points achieve the average power consumption goals. Next, this method tests each of the integrated circuit chips, and records the temperature cut points in the memory of the integrated circuit chips.

CROSS-REFERENCE TO RELATED APPLICATIONS

The disclosure is a continuation-in-part of currently pending U.S. patent application Ser. No. 13/484,451 filed on May 31, 2012, the entire teachings of which are incorporated herein by reference.

BACKGROUND

1. Field of the Invention

The disclosure generally relates to power and timing optimization of an integrated circuit (IC) chip, using an IC technology that exhibits temperature inversion, by modifying a voltage supplied to the IC chip, while meeting power consumption and timing delay performances across lower and higher temperature ranges.

2. Description of Related Art

Manufacturers of integrated circuits (ICs) seek to reduce not only the size of ICs, but also their power consumption. Power consumption of digital integrated circuits consists of two components: dynamic power consumption, associated with active operation of the circuit; and static power consumption, associated with leakage current when the circuit is inactive. Dynamic power consumption refers to the amount of power required to operate a digital circuit, e.g., a logic circuit or latch, and is proportional to value of the supply voltage squared and the frequency of operation. Static power consumption refers to the amount of power consumed by the digital circuit when it is inactive, and is an exponential function of the digital circuit's temperature and voltage.

Digital ICs frequently include a number of standard cells, i.e., standardized digital IC logic circuits or latches, which are characterized by cell libraries. The cell libraries of, for example, a Liberty model, are used during the design phase for the digital ICs and store various operating parameters, e.g., voltage, temperature, timing delay and power consumption ranges.

During the design phase of an IC chip, the cells and their interconnecting pathways may be analyzed in a multidimensional parameterized space, which includes voltage and temperature parameters, to provide a closed timing analysis for the IC chip. A timing performance, as measured by a timing delay, is selected for the IC design from the closed timing analysis.

The manufacture of IC chips to a single IC chip design will result in timing variations among the manufactured IC chips that result from variations of manufacturing process parameters, e.g., chemical mechanical polishing, optical proximity effects, random dopant effects, line-edge roughness, dose and focus variation. Variations in the manufacturing processes can introduce timing variations across chips of a single wafer or across chips from different wafers. Thus, in a population of IC chips manufactured to a single IC chip design, there will be a statistical distribution of subpopulations of IC chips that show smaller timing delays, i.e., fast IC chips, and larger timing delays, i.e., slow IC chips.

During operation, cells of IC chips manufactured from IC technologies, which exhibit temperature inversion, are associated with a negative coefficient of delay with respect to temperature. Thus, as temperatures increase for the cells of an IC chip exhibiting temperature inversion, the timing delay becomes smaller. In contrast, IC chips manufactured from IC technologies, which do not exhibit temperature inversion, show greater timing delays with increasing temperature.

At lower temperatures, cells of an IC chip using an IC technology that shows temperature inversion will have a greater timing delay. When supplied with a low driving voltage, these IC chips may not meet a timing delay performance. To meet a requirement for the timing delay performance, the IC chips can be driven at a high voltage at the lower temperatures. However, driving the IC chips at a high voltage results in increased dynamic and static power consumption. Alternatively, only those IC chips having a sufficiently high performance at the lower temperatures may be selected from a population of manufactured IC chips to meet the timing delay performance. This selection necessarily results in a smaller number of IC chips that are available.

At higher temperatures, cells using an IC technology that shows temperature inversion will show both increased dynamic and static power consumption, because voltage needs to be raised in order to meet performance at low temperature. This increased voltage causes higher active and leakage power.

There remains a need to optimize power and timing of an integrated circuit (IC) chip, using an IC technology that exhibits temperature inversion, by modifying a voltage supplied to the IC chip, while meeting power and timing delay performances across lower and higher temperature ranges.

SUMMARY

In view of the foregoing, an exemplary embodiment of the disclosure may provide a method of optimizing power and timing for an integrated circuit (IC) chip by modifying a voltage supplied to the IC chip, while meeting power consumption and timing delay performances across lower and higher temperature ranges. The method may include selecting a high voltage to be supplied to all of the cells of the IC chip that use an IC technology, which exhibits temperature inversion. The high voltage may meet the timing delay performance of a closed timing analysis for the IC chip across a full temperature range for all operation. The full temperature range may be divided into a lower temperature range and a higher temperature range, where the high voltage meets the power consumption performance across the lower temperature range and a portion of the higher temperature range extending from a lower bound of the higher temperature range to a temperature cut point within a range of temperature cut points in the higher temperature range. The method may also include selecting a low voltage to be supplied to all of the cells of the IC chip. The low voltage may meet the timing delay performance and the power consumption performance from the temperature cut point to an upper bound of the higher temperature range. The method may further include powering-on all of the cells of the IC chip at the high voltage, and monitoring a temperature of the IC chip after power-on. The method may yet further include lowering the high voltage supplied to all of the cells of the IC chip to the low voltage, when the temperature cut point is exceeded, to meet the power consumption performance while meeting the timing delay performance.

Another exemplary embodiment of the disclosure may provide a computer-implemented method of designing a system, including an integrated circuit (IC) chip, that optimizes power and timing for an integrated circuit (IC) chip by modifying a voltage supplied to the IC chip, while meeting power consumption and timing delay performances across lower and higher temperature ranges. The method may include selecting the timing delay performance of the IC chip, where all of the cells of the IC chip use an IC technology that exhibits temperature inversion. The selection of the timing delay performance may result from a closed timing analysis of all of the cells of the IC chip over a multi-dimensional parameterized space, including a high voltage being applied across a full temperature range, which may be divided into a lower temperature range and a higher temperature range, and a low voltage being applied across the higher temperature range. The method may also include selecting the power consumption performance of the IC chip. The selection of the power consumption performance may result from a closed timing analysis of all of the cells of said IC chip over a multi-dimensional parameterized space, including the high voltage being applied across the lower temperature range and a portion of the higher temperature range extending from a lower bound of the higher temperature range to a temperature cut point within the higher temperature range, and the low voltage being applied from the temperature cut point to an upper bound of the higher temperature range. The method may further include selecting a high voltage to be supplied to all of the cells of the IC chip. The high voltage may meet the timing delay performance for the IC chip across the full temperature range, which may be divided into a lower temperature range and a higher temperature range. The high voltage may meet the power consumption performance across the lower temperature range and a portion of the higher temperature range extending from a lower bound of the higher temperature range to a temperature cut point within a range of temperature cut points in the higher temperature range. The method may yet further include selecting a low voltage to be supplied to all of the cells of the IC chip. The low voltage may meet the timing delay performance and the power consumption performance from the temperature cut point to an upper bound of the higher temperature range. The method may yet further include selecting the temperature cut point from the range of temperature cut points having a lowermost value adjacent to an upper bound of the lower temperature range, where the high voltage being lowered to the low voltage maintains the timing delay performance for the IC chip, and an uppermost value, where the high voltage being lowered to the low voltage is required to meet the power consumption performance for the IC chip. The method may yet further include assigning the high voltage to be supplied to all of the cells of the IC chip by a voltage regulator of the system, upon powering-on said system, and assigning the low voltage to be supplied to all of the cells of the IC chip by the voltage regulator, when a temperature of the IC chip monitored by a temperature monitor of the system indicates the temperature cut point is exceeded.

Yet another exemplary embodiment of the disclosure may provide a non-transitory computer program storage device readable by a computer, tangibly embodying a program of instructions executable by the computer to perform a method of optimizing power and timing for an integrated circuit (IC) chip by modifying a voltage supplied to the IC chip, while meeting power consumption and timing delay performances across lower and higher temperature ranges. The method may include selecting a high voltage to be supplied to all of the cells of the IC chip that use an IC technology, which exhibits temperature inversion. The high voltage may meet the timing delay performance of a closed timing analysis for the IC chip across a full temperature range for all operation. The full temperature range may be divided into a lower temperature range and a higher temperature range, where the high voltage meets the power consumption performance across the lower temperature range and a portion of the higher temperature range extending from a lower bound of the higher temperature range to a temperature cut point within a range of temperature cut points in the higher temperature range. The method may also include selecting a low voltage to be supplied to all of the cells of the IC chip. The low voltage may meet the timing delay performance and the power consumption performance from the temperature cut point to an upper bound of the higher temperature range. The method may further include powering-on all of the cells of the IC chip at the high voltage, and monitoring a temperature of the IC chip after power-on. The method may yet further include lowering the high voltage supplied to all of the cells of the IC chip to the low voltage, when the temperature cut point is exceeded, to meet the power consumption performance while meeting the timing delay performance.

Yet another exemplary embodiment of the disclosure may prove a method that optimizes power and timing by modifying a voltage supplied to each of a population of integrated circuit (IC) chips, while meeting power consumption and timing delay performances for each of the population of IC chips across lower and higher temperature ranges. The method may include conducting a closed timing analysis on an IC chip design, using an IC technology that exhibits temperature inversion, to select the timing delay performance over a multi-dimensional parameterized space, including a higher voltage range being applied across a full temperature range, which may be divided into a lower temperature range and a higher temperature range, and a lower voltage range being applied across the higher temperature range. The method may also include segmenting the full temperature range into N selective voltage bins, each of the population of IC chips, manufactured to the IC chip design, belonging to one of the N selective voltage bins and each of the N selective bins being associated with a high bin voltage and a low bin voltage. The method may further include selecting each of the high bin voltages for each of the N selective voltage bins from the higher voltage range to be supplied to each of the population of IC chips in corresponding ones of the N selective voltage bins. Each of the high bin voltages for each of the N selective voltage bins may meet the timing delay performance across the full temperature range and the power consumption performance across the lower temperature range and a portion of the higher temperature range extending from a lower bound of the higher temperature range to a temperature cut point within a range of temperature cut points in the higher temperature range. The method may yet further include selecting each of the low bin voltages for each of the N selective voltage bins from the lower voltage range to be supplied to each of the population of IC chips in the corresponding ones of the N selective voltage bins. Each of the low bin voltages for each of the N selective voltage bins may meet the timing delay performance and the power consumption performance from the temperature cut point to an upper bound of the higher temperature range. The method may yet further include powering-on each of the population of IC chips in each of the corresponding ones of the N selective voltage bins at each of the high bin voltages for each of the N selective voltage bins, and monitoring a temperature of each of the population of IC chips after powering-on. The method may yet further include lowering the high bin voltage supplied to each of the population of IC chips in each of the corresponding ones of the N selective voltage bins to the low bin voltage for each of the corresponding ones of the N selective voltage bins, when the temperature cut point is exceeded for each of the population of IC chips in each of the corresponding ones of the N selective voltage bins, to meet the power consumption performance while meeting the timing delay performance.

Another method herein begins with inputs of the average power consumption goals and timing delay goals for an integrated circuit chip design. The integrated circuit chips produced according to such an integrated circuit chip design exhibit temperature inversion, meaning such chips have decreasing timing delay (such chips speed up) as operating temperature increases.

Then, the method identifies, for each of the integrated circuit chips, a plurality of “valid” temperature and voltage combinations that allow the integrated circuit chip to operate within the timing delay goals. Additionally, selective voltage bins are established for the integrated circuit chips. Each different selective voltage bin represents a different part of the allowed process window from fast to slow for the integrated circuit chips. Each of the integrated circuit chips will be assigned to one of the selective voltage bins, based on measurement of ring oscillators in the product. These ring oscillators identify the speed of the product and predict the timing delay of the integrated circuit chips. Leakage is highest at the fast end of the performance window and decreases at slower parts of the performance window. Faster parts are operated at lower voltage and slower parts are operated at higher voltage.

The method also selects temperature cut points from the valid temperature and voltage combinations for each of the selective voltage bins using the computerized device. Each pair of temperature cut points defines a temperature range that is bounded by the temperature cut points (or a temperature range that is unbounded on one end, for the highest and lowest temperature ranges). The temperature cut points direct each integrated circuit chip to operate at a corresponding operating voltage when the integrated circuit chip has a temperature within a corresponding temperature range defined by the temperature cut points. The temperature cut points are selected to cause each of the integrated circuit chips to individually satisfy (on average) the average power consumption goals.

This method also calculates, for each of the temperature cut points of each of the selective voltage bins, a power consumption amount based on the valid temperature and voltage combinations of each of the temperature cut points within each of the selective voltage bins, using the computerized device. Then, this method iteratively adjusts the temperature cut points based on the power consumption amount calculated (and recalculates a new power consumption amount in each iteration of new temperature cut points) until the temperature cut points achieve the average power consumption goals.

Device leakage models are used to create test static power disposition criteria at test voltage and temperature that corresponds to system power consumption objectives. This method tests each integrated circuit chip at a designated temperature(s) and designated voltage(s) (using testing equipment operatively connected to a computerized device) to determine performance (timing delay), and static (leakage) power consumption. Thus, performance (timing delay) test results, and static power consumption test results are produced for each integrated circuit chip at test temperature and voltage. The “static” power consumption is associated with leakage current of each the integrated circuit chip. The total power consumption of a given integrated circuit is the sum of the dynamic power consumption and the static power consumption. Both static and dynamic power are reduced as voltage is lowered.

Next, once the integrated circuit chips are tested, this exemplary method sorts the integrated circuit chips into selective voltage bins based on the ring oscillator test results. An identifier corresponding to the each process window segment is recorded in a memory in each integrated circuit chip.

Once binned, the method can then record (in a memory of each integrated circuit chips) the multiple temperature cut points corresponding to a combination of average power consumption goal and timing delay goal of the bin into which each of the integrated circuit chips has been sorted. During in-service operations each of the integrated circuit chips alters their current operating voltage based on the current selective voltage bin identifier, the operating temperature and the temperature cut points in the memory.

In addition, the methods herein can determine a percentage of the integrated circuit chips that were sorted into each of the voltage bins, and determine the amount of time each of the integrated circuit chip will be operating within each different temperature range defined by the temperature cut points. With this information, the methods herein can calculate average system power consumption of all chips manufactured according to the integrated circuit design (or within a certain voltage bin). The average system power is based on the product of the percentage of integrated circuit chips sorted into each of the voltage bins, the amount of time each of the integrated circuit chip will be operating within each different temperature range defined by the temperature cut points, and the power consumption amount of each of the temperature cut points of each of the voltage bins.

BRIEF DESCRIPTION OF THE DRAWINGS

The embodiments herein will be better understood from the following detailed description with reference to the drawings, which are not necessarily drawn to scale and in which:

FIG. 1A is a schematic diagram illustrating a high voltage being lowered to a low voltage for an IC chip exhibiting temperature inversion at a temperature cut point as the temperature of the IC chip increases in an exemplary embodiment;

FIG. 1B is a schematic diagram illustrating a low voltage being increased to a high voltage for an IC chip exhibiting temperature inversion at a temperature cut point as the temperature of the IC chip decreases in an exemplary embodiment;

FIG. 2 is a flowchart illustrating a method of optimizing power and timing for an IC chip by modifying a voltage supplied to the IC chip, while meeting power consumption and timing delay performances across lower and higher temperature ranges in an exemplary embodiment;

FIG. 3 is a flowchart illustrating a computer-implemented method of designing a system, including an IC chip, that optimizes power and timing for the IC chip by modifying a voltage supplied to the IC chip, while meeting power consumption and timing delay performances across lower and higher temperature ranges in an exemplary embodiment;

FIG. 4 is a flowchart illustrating a method that optimizes power and timing by modifying a voltage supplied to each of a population of IC chips, while meeting power consumption and timing delay performances for each of said population of IC chips across lower and higher temperature ranges in an exemplary embodiment;

FIG. 5 is a flowchart illustrating a computer-implemented method of designing a system that optimizes power and timing by modifying a voltage supplied to each of a population of IC chips, while meeting power consumption and timing delay performances for each of said population of IC chips across lower and higher temperature ranges in an exemplary embodiment;

FIG. 6 is a flowchart illustrating a method of embodiments herein;

FIG. 7 is a flowchart illustrating a method of embodiments herein;

FIG. 8 is a schematic diagram of a hardware system according to embodiments herein;

FIG. 9 is a schematic diagram of a deployment system according to embodiments herein;

FIG. 10 is a schematic diagram of an integration system according to embodiments herein;

FIG. 11 is a schematic diagram of an on demand system according to embodiments herein;

FIG. 12 is a schematic diagram of a virtual private network system according to embodiments herein; and

FIG. 13 is a schematic diagram of a virtual private network system according to embodiments herein.

DETAILED DESCRIPTION

The exemplary embodiments of the disclosure and their various features and advantageous details are explained more fully with reference to the non-limiting exemplary embodiments that are illustrated in the accompanying drawings and detailed in the following description. It should be noted that the features illustrated in the drawings are not necessarily drawn to scale. Descriptions of well-known materials, components, and processing techniques are omitted so as to not unnecessarily obscure the exemplary embodiments of the disclosure. The examples used herein are intended to merely facilitate an understanding of ways in which the exemplary embodiments of the disclosure may be practiced and to further enable those of skill in the art to practice the exemplary embodiments of the disclosure. Accordingly, the examples should not be construed as limiting the scope of the exemplary embodiments of the disclosure.

As described above, there remains a need to optimize power and timing of an integrated circuit (IC) chip, using an IC technology that exhibits temperature inversion, by modifying a voltage supplied to the IC chip, while meeting power consumption and timing delay performances across lower and higher temperature ranges.

Various exemplary embodiments of the disclosure may take advantage of the negative temperature coefficient for a timing delay exhibited by a IC chip, by selecting a high voltage to be supplied to the IC chip over a lower temperature range to overcome a poor timing delay performance, while meeting a power consumption performance, and by selecting a low voltage to be supplied to the IC chip over a higher temperature range to reduce increased power consumption, while meeting the timing delay performance.

FIG. 1A schematically illustrates the operation of an IC chip, which exhibits temperature inversion, as the temperature of the IC chip increases over a full temperature range, extending from a lowest possible operating temperature to a highest possible operating temperature in an exemplary embodiment. A closed timing analysis over a multidimensional parameterized space may provide a high voltage that meets a selected timing delay performance for the IC chip over a lower temperature range, which is associated with the major portion of the impact of temperature inversion, while meeting a power consumption performance. However, as the temperature increases to a higher temperature range for the IC chip at the high voltage, the power consumption may increase beyond that associated with the highest value of power consumption for the lower temperature range. Lowering the high voltage supplied to the IC chip at a temperature cut point 110 may reduce the higher power consumption within the higher temperature range, while still meeting the timing delay performance. Thus, temperature cut point 110 may represent the lowest temperature within the higher temperature range, where the high voltage may be lowered and still meet the timing delay performance.

The high voltage supplied to the IC chip at temperatures higher than that of the temperature cut point 110 may be maintained over a range of temperature cut points that meet both the timing delay and power consumption performances. As the temperature increases beyond the temperature cut point 110, power consumption increases until at temperature cut point 120, the power consumption performance may be exceeded. Thus, temperature cut point 120 may represent the highest temperature of the range of temperature cut points, where the high voltage must be lowered to meet the power consumption performance. The temperature cut point range, which extends from the temperature cut point 110 to the temperature cut point 120, meets both the timing delay and power consumption performances for the IC chip with either the high or low supply voltages.

FIG. 1B schematically illustrates the operation of an IC chip, which exhibits temperature inversion, as the temperature of the IC chip decreases over a full temperature range, extending from a highest possible operating temperature to a lowest possible operating temperature in an exemplary embodiment. As the temperature decreases over the higher temperature range, temperature cut point 120 may now represent lowest temperature in the higher temperature range, where either the low or the high supply voltage may meet the power consumption performance, while still meeting the timing performance, and temperature cut point 110 may represent lowest temperature of the higher temperature range, where the low voltage must be increased to the high voltage to meet the timing delay performance.

For given timing delay and power consumption performances, the range of temperature cut points for an IC chip exhibiting temperature inversion will be the same for increasing and decreasing temperatures. However, the selection of a particular temperature cut point within the range of temperature cut points for rising temperatures need not be the same as that for decreasing temperatures. As a first temperature cut point for rising temperatures will be associated with a transition from a high to a low supply voltage in the IC chip, whereas a second temperature cut point for decreasing temperatures will be associated with a transition from a low to a high supply voltage, a simple logic circuit may affect the supply voltage transitions at the first and second temperature cut points.

FIG. 2 illustrates a flow chart 290 of method of optimizing power and timing for an IC chip by modifying a voltage supplied to the IC chip, while meeting power consumption and timing delay performances across lower and higher temperature ranges in an exemplary embodiment. The method may be applied to all cells of the IC chip, which uses an IC technology that exhibits temperature inversion.

Referring to FIG. 2, the method may include selecting a high voltage to be supplied to all cells of the IC chip, in which the high voltage meets a timing delay performance for the IC chip across a full operating temperature range. The full operating temperature range may be divided into a lower temperature range and a high temperature range, which is adjacent to the lower temperature range. The high voltage may further meet a power consumption performance of the IC chip across the lower temperature range and a portion of the higher temperature range extending from a lower bound of the higher temperature range to a temperature cut point within a range of temperature cut points in the higher temperature range, 291. The selecting of the high voltage may result from a closed timing analysis that provides the timing delay and power consumption performances for the IC chip over a multi-dimensional parameterized space, including voltage parameters being applied across the full temperature range, the lower temperature range, and the higher temperature range. The range of temperature cut points may include a lowermost value adjacent to the upper bound of the lower temperature range, where the high supply voltage being lowered to the low supply voltage maintains the timing delay performance of the IC chip, and an uppermost value, where the high supply voltage being lowered to the low supply voltage may be required to meet the power consumption performance of the IC chip. The temperature cut point may result from a closed timing analysis that provides the timing delay performance and power consumption performances for the IC chip over a multi-dimensional parameterized space, including temperature parameters from the higher temperature range being applied across both the selected high voltage and low voltage.

The method may also include selecting a low voltage to be supplied to all of the cells of the IC chip, in which the low voltage meets the timing delay performance and the power consumption performance from the temperature cut point to an upper bound of the higher temperature range, 292. The selecting of the low voltage may result from a closed timing analysis that provides the timing delay and power consumption performances for the IC chip over a multi-dimensional parameterized space, including voltage parameters being applied across the higher temperature range, including the range of temperature cut points.

The method may further include powering-on all of the cells of the IC chip at the high voltage, 293, and monitoring a temperature of the IC chip after the powering-on, 294. The method may yet further include lowering the high voltage supplied to all of the cells of the IC chip to the low voltage, when the temperature cut point is exceeded, to meet the power consumption performance while meeting the timing delay performance, 295.

The method may yet further include increasing the low voltage supplied to all of the cells of the IC chip to the high voltage, when the temperature of the IC chip decreases below the temperature cut point, to meet the timing delay performance while meeting the power consumption performance, 296.

The method of optimizing power and timing for an IC chip by modifying a voltage supplied to the IC chip, while meeting power consumption and timing delay performances across lower and higher temperature ranges, which is embodied by flowchart 290 of FIG. 2 may reside in non-transitory computer program storage device readable by a computer, tangibly embodying a program of instructions executable by the computer to perform the method.

FIG. 3 illustrates a flow chart 300 of a computer-implemented method of designing a system that optimizes power and timing for an IC chip by modifying a voltage supplied to the IC chip, while meeting power consumption and timing delay performances across lower and higher temperature ranges in an exemplary embodiment. The method of design may be applied to a system including: the IC chip, in which all cells of the IC chip use an IC technology that exhibits temperature inversion; a temperature monitor that monitors the temperature of the IC chip; and a voltage regulator that provides one of a high supply voltage and a low supply voltage to the IC chip, according to temperature information received from the temperature monitor in an exemplary embodiment.

Referring to FIG. 3, the method may include selecting the timing delay performance of the IC chip from results of a closed timing analysis of all of the cells of the IC chip over a multi-dimensional parameterized space, including a high voltage of a voltage range being applied across a full operating temperature range, in which the full operating temperature range is divided into a lower temperature range and a higher temperature range, and a low voltage of the voltage being applied across the higher temperature range, 310.

The method may also include selecting the power consumption performance of the IC chip from results of the closed timing analysis of all of the cells of the IC chip, in which power consumption performance is related to both the voltage and the temperature parameters of the multi-dimensional parameterized space for each of the timing performances of each of the cells in the closed timing analysis. The analysis including the high voltage being applied across the lower temperature range and a portion of the higher temperature range extending from a lower bound of the higher temperature range to a temperature cut point within the higher temperature range, and the low voltage being applied from the temperature cut point to an upper bound of the higher temperature range, 320.

The method may yet further include selecting the temperature cut point from the closed timing analysis that provides the timing delay performance and power consumption performances for the IC chip over a multi-dimensional parameterized space, including temperature parameters from the higher temperature range being applied across a voltage range including both a selected high voltage and low voltage, 330. The temperature cut point may be disposed in a range of temperature cut points that includes a lowermost value adjacent to an upper bound of the lower temperature range, where the high supply voltage being lowered to the low supply voltage of the IC chip maintains the timing delay performance, and an uppermost value, where the high supply voltage being lowered to the low supply voltage is required to meet the power consumption performance of the IC chip.

The method may further include selecting the high voltage to be supplied to all of the cells of the IC chip, in which the high voltage meets the timing delay performance for the IC chip across the full operating temperature range. The full operating temperature range may be divided into a lower temperature range and a high temperature range, which is adjacent to the lower temperature range. The high voltage may meet the power consumption performance across the lower temperature range and a portion of the higher temperature range extending from a lower bound of the higher temperature range to a temperature cut point within a range of temperature cut points in the higher temperature range, 340. The selecting of the high voltage may result from a closed timing analysis that provides the timing delay and power consumption performances for the IC chip over a multi-dimensional parameterized space, including voltage parameters being applied across the full temperature range, the lower temperature range, and the higher temperature range.

The method may yet further include selecting the low voltage to be supplied to all of the cells of the IC chip, in which the low voltage meets the timing delay performance and the power consumption performance from the temperature cut point to an upper bound of the higher temperature range, 350.

The method may yet further include assigning the high voltage to be supplied to all of the cells of the IC chip by a voltage regulator of the system, upon powering-on the system, 360, and assigning the low voltage to be supplied to all of the cells of the IC chip by the voltage regulator, when a temperature of the IC chip monitored by a temperature monitor of the system indicates the temperature cut point is exceeded, 370.

The method may yet further include assigning the high voltage to be supplied to all of the cells of the IC chip by the voltage regulator, when the temperature of the IC chip being supplied by the low voltage, decreases below the temperature cut point, as indicated by the temperature monitor, 380.

The method of a computer-implemented method of designing a system that optimizes power and timing for an IC chip by modifying a voltage supplied to the IC chip, while meeting power consumption and timing delay performances across lower and higher temperature ranges, which is embodied by flowchart 300 of FIG. 3 may reside in non-transitory computer program storage device readable by a computer, tangibly embodying a program of instructions executable by the computer to perform the method.

FIG. 4 illustrates a flow chart 400 of method that optimizes power and timing by modifying a voltage supplied to each of a population of IC chips, while meeting power consumption and timing delay performances for each of the population of IC chips across lower and higher temperature ranges in an exemplary embodiment. The method may be applied to each of the population of IC chips that use an IC technology that exhibits temperature inversion.

The method may include conducting a closed timing analysis on an IC chip design to select the timing delay performance over a multi-dimensional parameterized space, including a higher voltage range being applied across a full temperature range, which is divided into a lower temperature range and a higher temperature range, and a lower voltage range being applied across the higher temperature range, 405.

The method may also include segmenting a full range of the performance into N selective voltage bins, where each of the population of IC chips, manufactured to the IC chip design, may belong to one of the N selective voltage bins. Each of the selective voltage bins may be associated with a high bin voltage and a low bin voltage, 410. Selective voltage binning is well known in the art for IC chips that use an IC technology, which does not exhibit temperature inversion, and involves dividing a population of IC chips into bins according to their operating speeds. Relatively fast IC chips with high operating speeds will operate at lower voltages to keep the operating speeds and power consumption approximately equal to relatively slow IC chips. In the exemplary embodiment, selective voltage binning may be applied to the population of IC chips that use an IC technology that exhibits temperature inversion.

The method may further include selecting each of the high bin voltages for each of the N selective voltage bins from the higher voltage range to be supplied to each of the population of IC chips in corresponding ones of the N selective voltage bins, 415. Each of the high bin voltages for each of the N selective voltage bins may meet the timing delay performance for each of the population of IC chips in the corresponding ones of the N selective voltage bins across the full temperature range, and the power consumption performance for each of the population of IC chips in the corresponding ones of the N selective voltage bins across the lower temperature range and a portion of the higher temperature range extending from a lower bound of the higher temperature range to a temperature cut point within a range of temperature cut points in the higher temperature range.

The method may yet further include selecting each of the low bin voltages for each of the N selective voltage bins from the lower voltage range to be supplied to each of the population of IC chips in the corresponding ones of the N selective voltage bins, 420. Each of the low bin voltages for each of the N selective voltage bins may meet the timing delay performance and the power consumption performance for each of the population of IC chips in the corresponding ones of the N selective voltage bins from the temperature cut point to an upper bound of the higher temperature range.

The method may yet further include powering-on each of the population of IC chips in each of the corresponding ones of the N selective voltage bins at each of the high bin voltages for each of the N selective voltage bins, 425, and monitoring a temperature of each of the population of IC chips after powering-on, 430.

The method may yet further include lowering the high bin voltage supplied to each of the population of IC chips in each of the corresponding ones of the N selective voltage bins to the low bin voltage for each of the corresponding ones of the N selective voltage bins, when the temperature cut point is exceeded for each of the population of IC chips in each of the corresponding ones of the N selective voltage bins, to meet the power consumption performance while meeting the timing delay performance, 435.

The method may yet further include increasing the low bin voltage supplied to each of the population of IC chips in each of the corresponding ones of the N selective voltage bins, to the high voltage, when the temperature of each of the population of IC chips in each of the corresponding ones of the N selective voltage bins decreases below the temperature cut point, to meet the timing delay performance while meeting the power consumption performance, 440.

The method that optimizes power and timing by modifying a voltage supplied to each of a population of integrated circuit (IC) chips, while meeting power consumption and timing delay performances for each of said population of IC chips across lower and higher temperature ranges, which is embodied by flowchart 400 of FIG. 4 may reside in non-transitory computer program storage device readable by a computer, tangibly embodying a program of instructions executable by the computer to perform the method.

FIG. 5 illustrates a flow chart 500 of a computer-implemented method of designing a system that optimizes power and timing by modifying a voltage supplied to each of a population of integrated circuit (IC) chips, while meeting power consumption and timing delay performances for each of said population of IC chips across lower and higher temperature ranges in an exemplary embodiment. The method of design may be applied to a system including: a population of IC chips that have been segmented into N selective voltage bins and where each of the population of IC chips uses an IC technology that exhibits temperature inversion; a plurality of temperature monitors that monitor the temperature of each of the population of IC chips belonging to one of the N selective voltage bins; a multi-port voltage regulator that provides one of a high bin voltage and a low bin voltage to each of the population of IC chips belonging to one of the N selective voltage bins; and a logic circuit that receives temperatures from each of the plurality of temperature monitors and compares each of the temperatures received from each of the population of IC chips belonging to one of the N selective voltage bins to a temperature cut point to determine whether the high bin voltage or the low bin voltage should be supplied by the multi-port voltage regulator to each of the population of IC chips belonging to one of the N selective voltage bins in an exemplary embodiment.

Referring to FIG. 5, the method may include selecting a timing delay performance from a closed timing analysis of an IC chip design to be used for the population of IC chips. The closed timing analysis may be conducted over a multi-dimensional parameterized space, including a higher voltage range being applied across a full temperature range, which is divided into a lower temperature range and a higher temperature range, and a lower voltage range being applied across the higher temperature range, 505.

The method may also include selecting the power consumption performance of the population of IC chips from results of the closed timing analysis of the IC chip design, including the higher voltage range being applied across the lower temperature range and a portion of the higher temperature range extending from a lower bound of the higher temperature range to a temperature cut point within the higher temperature range, and the lower voltage range being applied from the temperature cut point to an upper bound of the higher temperature range, 510.

The method may further include selecting the temperature cut point from the closed timing analysis that provides the timing delay performance and power consumption performances for the IC chip design over a multi-dimensional parameterized space, including temperature parameters from the higher temperature range being applied across both the selected higher voltage range and lower voltage range, 515.

The method may yet further include segmenting a full range of the timing delay performance into N selective voltage bins, where each of the population of IC chips, manufactured to the IC chip design, may belong to one of the N selective voltage bins. Each of the selective voltage bins may be associated with a high bin voltage and a low bin voltage, 520.

The method may further include selecting each of the high bin voltages for each of the N selective voltage bins from the higher voltage range to be supplied to each of the population of IC chips in corresponding ones of the N selective voltage bins, 525. Each of the high bin voltages for each of the N selective voltage bins may meet the timing delay performance for each of the population of IC chips in the corresponding ones of the N selective voltage bins across the full temperature range, and the power consumption performance for each of the population of IC chips in the corresponding ones of the N selective voltage bins across the lower temperature range and a portion of the higher temperature range extending from a lower bound of the higher temperature range to a temperature cut point within a range of temperature cut points in the higher temperature range.

The method may yet further include selecting each of the low bin voltages for each of the N selective voltage bins from the lower voltage range to be supplied to each of the population of IC chips in the corresponding ones of the N selective voltage bins, 530. Each of the low bin voltages for each of the N selective voltage bins may meet the timing delay performance and the power consumption performance for each of the population of IC chips in the corresponding ones of the N selective voltage bins from the temperature cut point to an upper bound of the higher temperature range.

The method may yet further include assigning each of the high bin voltages for each of the N selective voltage bins to power-on each of the population of IC chips in each of the corresponding ones of the N selective voltage bins, to meet the timing delay performance while meeting the power consumption performance, 535, and assigning each of the low bin voltages for each of the N selective voltage bins to be supplied to each of the population of IC chips in each of the corresponding ones of the N selective voltage bins, when the temperature cut point is exceeded for each of the population of IC chips in each of the corresponding ones of the N selective voltage bins, to meet the power consumption performance while meeting the timing delay performance, 540.

The method may yet further include increasing the low bin voltage supplied to each of the population of IC chips in each of the corresponding ones of the N selective voltage bins, to the high voltage, when the temperature of each of the population of IC chips in each of the corresponding ones of the N selective voltage bins decreases below the temperature cut point, to meet the timing delay performance while meeting the power consumption performance, 545.

The method that optimizes power and timing by modifying a voltage supplied to each of a population of integrated circuit (IC) chips, while meeting power consumption and timing delay performances for each of said population of IC chips across lower and higher temperature ranges, which is embodied by flowchart 500 of FIG. 5 may reside in non-transitory computer program storage device readable by a computer, tangibly embodying a program of instructions executable by the computer to perform the method.

As also shown in flowchart form in FIG. 6, one method herein begins with inputs of the average power consumption goals and timing delay goals for an integrated circuit chip design (item 600). The integrated circuit chips produced according to such an integrated circuit chip design exhibit temperature inversion, meaning such chips have decreasing timing delay (such chips speed up) as operating temperature increases.

Then, in item 602, the method identifies, for each of the integrated circuit chips, a plurality of “valid” temperature and voltage combinations that allow the integrated circuit chip to operate within the timing delay goals. Additionally, in item 604, selective voltage bins for the integrated circuit chips are selected or input. Each different voltage bin represents a segment of the allowed process window. Each of the integrated circuit chips will be assigned to or sorted into one of the selective voltage bins, based on ring oscillator measurements that correlate with the timing delay of the integrated circuit chips.

The method also selects temperature cut points from the valid temperature and voltage combinations for each of the selective voltage bins using the computerized device in item 606. Each pair of temperature cut points defines a temperature range that is bounded by the temperature cut points (or a temperature range that is unbounded on one end, for the highest and lowest temperature ranges). The temperature cut points direct each integrated circuit chip to operate at a corresponding operating voltage when the integrated circuit chip has a temperature within a corresponding temperature range defined by the temperature cut points. The temperature cut points are selected to cause each of the integrated circuit chips to individually satisfy (on average) the average power consumption goals.

This method also calculates, for each of the temperature cut points of each of the selective voltage bins, a power consumption amount. This power consumption amount is based on the valid temperature and voltage combinations of each of the temperature cut points within each of the voltage bins, using the computerized device, in item 608. Then, in item 610 this method iteratively adjusts the temperature cut points based on the power consumption amount calculated (and recalculates a new power consumption amount in each iteration of new temperature cut points) until the temperature cut points achieve the average power consumption goals.

This method then tests each integrated circuit chip at a designated temperature(s) and voltage(s) in item 612 (using testing equipment operatively connected to a computerized device).

Next, in item 614, once the integrated circuit chips are tested, this exemplary method can automatically sort the integrated circuit chips into the selective voltage bins based on the ring oscillator (timing delay test) results.

Once binned, in item 616, the method can then automatically record (in a memory of the integrated circuit chips) the selective voltage bin identifier and the multiple temperature cut points corresponding to a combination of average power consumption goal and timing delay goal into which each of the integrated circuit chips has been sorted. During in-service operations each of the integrated circuit chips alters their current operating voltage based on the current operating temperature and the temperature cut points in the memory.

In addition, the methods herein can determine a percentage of the integrated circuit chips that were sorted into each of the voltage bins (item 620), and determine the amount of time each of the integrated circuit chip will be operating within each different temperature range defined by the temperature cut points (item 622). With this information and the allowed temperature/voltage combination for each planned bin (item 608), the methods herein can calculate average system power consumption of all chips manufactured according to the integrated circuit design (or within a certain voltage bin) in item 624. The average system power found in item 624 is based on the product of the percentage of integrated circuit chips sorted into each of the voltage bins, the amount of time each of the integrated circuit chip will be operating within each different temperature range defined by the temperature cut points, and the power consumption amount of each of the temperature cut points of each of the voltage bins.

Then in item 626, the system voltage is set based on selective voltage bin identifier and temperature. During power up, each integrated circuit product uses the highest allowed voltage. Temperature in the product is measured and if the temperature is lower than the designated cut point, the voltage is lowered.

When the product has a high activity (high switching factor), temperature increases. When the high activity increases the temperature above a designated temperature cut point, the voltage can be reduced to that identified by the temperature/voltage cutpoint. Lower voltage results in lower static power (leakage) and lower dynamic power. When the activity is lower, the temperature will be lower. When temperature is lowered below the temperature cutpoint, a higher voltage is needed to maintain system performance. For each selective voltage bin, system average power is the weight average of the power at each of the cutpoints and the time the system is at each of the cutpoints. Without this technique, voltage would remain at the higher voltage (and higher power) at all times. Applying different voltages for higher and lower temperature cutpoints reduces average system power.

FIG. 7 is similar to FIG. 6, but illustrates a process that does not involve selective voltage binning. The steps that are the same between FIGS. 6 and 7 are identified using the same numbering. However, in FIG. 7, the selection of the system design temperature cut points is simply done once for the integrated circuit chip design in item 656, and does not need to be done for each selective voltage bin as was done in item 606 in FIG. 6. Similarly, in item 658 the power consumption calculation is simply done once for each of the temperature cut points of the integrated circuit chip design, and does not need to be done for each temperature cut point in each selective voltage bin as was done in item 608 in FIG. 6. Because the chips are not sorted into selective voltage bins in the method shown in FIG. 7, the temperature cut points are simply recorded in the integrated circuit chips in item 666 (compare item 616 in FIG. 6). Also, item 624 is revised to item 674 in FIG. 7 to represent that the average system power is based on the product of the amount of time each of the integrated circuit chip will be operating within each different temperature range defined by the temperature cut points, and the power consumption amount of each of the temperature cut points (because, again, FIG. 7 represents a process that does not involve selective voltage binning).

As will be appreciated by one skilled in the art, aspects of the systems and methods herein may be embodied as a system, method or computer program product. Accordingly, aspects of the present disclosure may take the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, micro-code, etc.) or an embodiment combining software and hardware aspects that may all generally be referred to herein as a “circuit,” “module” or “system.” Furthermore, aspects of the present disclosure may take the form of a computer program product embodied in one or more computer readable medium(s) having computer readable program code embodied thereon.

Any combination of one or more computer readable non-transitory medium(s) may be utilized. The computer readable medium may be a computer readable signal medium or a computer readable storage medium. The non-transitory computer storage medium stores instructions, and a processor executes the instructions to perform the methods described herein. A computer readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of the computer readable storage medium would include the following: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of this document, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.

A computer readable signal medium may include a propagated data signal with computer readable program code embodied therein, for example, in baseband or as part of a carrier wave. Such a propagated signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination thereof. A computer readable signal medium may be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device.

Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

Computer program code for carrying out operations for aspects of the present disclosure may be written in any combination of one or more programming languages, including an object oriented programming language such as Java, Smalltalk, C++ or the like and conventional procedural programming languages, such as the “C” programming language or similar programming languages. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet Service Provider).

Aspects of the present disclosure are described below with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments herein. It will be understood that each block of the flowchart illustrations and/or two-dimensional block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks.

The computer program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other devices to cause a series of operational steps to be performed on the computer, other programmable apparatus or other devices to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide processes for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks.

A representative hardware environment for practicing the embodiments herein is depicted in FIG. 8. This schematic drawing illustrates a hardware configuration of an information handling/computer system in accordance with the embodiments herein. The system comprises at least one processor or central processing unit (CPU) 10. The CPUs 10 are interconnected via system bus 12 to various devices such as a random access memory (RAM) 14, read-only memory (ROM) 16, and an input/output (I/O) adapter 18. The I/O adapter 18 can connect to peripheral devices, such as disk units 11 and tape drives 13, or other program storage devices that are readable by the system. The system can read the inventive instructions on the program storage devices and follow these instructions to execute the methodology of the embodiments herein. The system further includes a user interface adapter 19 that connects a keyboard 15, mouse 17, speaker 24, microphone 22, and/or other user interface devices such as a touch screen device (not shown) to the bus 12 to gather user input. Additionally, a communication adapter 20 connects the bus 12 to a data processing network 25, and a display adapter 21 connects the bus 12 to a display device 23 which may be embodied as an output device such as a monitor, printer, or transmitter, for example.

The flowchart and block diagrams in the Figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments herein. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems that perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

The method as described above is used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.

Deployment types include loading directly in the client, server and proxy computers via loading a storage medium such as a CD, DVD, etc. The process software may also be automatically or semi-automatically deployed into a computer system by sending the process software to a central server or a group of central servers. The process software is then downloaded into the client computers that will execute the process software. The process software is sent directly to the client system via e-mail. The process software is then either detached to a directory or loaded into a directory by a button on the e-mail that executes a program that detaches the process software into a directory. Send the process software directly to a directory on the client computer hard drive. When there are proxy servers, the process will, select the proxy server code, determine on which computers to place the proxy servers' code, transmit the proxy server code, and then install the proxy server code on the proxy computer. The process software will be transmitted to the proxy server then stored on the proxy server.

While it is understood that the process software may be deployed by manually loading directly in the client, server and proxy computers via loading a storage medium such as a CD, DVD, etc., the process software may also be automatically or semi-automatically deployed into a computer system by sending the process software to a central server or a group of central servers. The process software is then downloaded into the client computers that will execute the process software. Alternatively the process software is sent directly to the client system via e-mail. The process software is then either detached to a directory or loaded into a directory by a button on the e-mail that executes a program that detaches the process software into a directory. Another alternative is to send the process software directly to a directory on the client computer hard drive. When there are proxy servers, the process will, select the proxy server code, determine on which computers to place the proxy servers' code, transmit the proxy server code, then install the proxy server code on the proxy computer. The process software will be transmitted to the proxy server then stored on the proxy server.

In FIG. 9, Step 100 begins the deployment of the process software. The first thing is to determine if there are any programs that will reside on a server or servers when the process software is executed 101. If this is the case then the servers that will contain the executables are identified 209. The process software for the server or servers is transferred directly to the servers' storage via FTP or some other protocol or by copying through the use of a shared file system 210. The process software is then installed on the servers 211.

Next, a determination is made on whether the process software is be deployed by having users access the process software on a server or servers 102. If the users are to access the process software on servers then the server addresses that will store the process software are identified 103.

A determination is made if a proxy server is to be built 200 to store the process software. A proxy server is a server that sits between a client application, such as a Web browser, and a real server. It intercepts all requests to the real server to see if it can fulfill the requests itself. If not, it forwards the request to the real server. The two primary benefits of a proxy server are to improve performance and to filter requests. If a proxy server is required then the proxy server is installed 201. The process software is sent to the servers either via a protocol such as FTP or it is copied directly from the source files to the server files via file sharing 202. Another embodiment would be to send a transaction to the servers that contained the process software and have the server process the transaction, then receive and copy the process software to the server's file system. Once the process software is stored at the servers, the users via their client computers, then access the process software on the servers and copy to their client computers file systems 203. Another embodiment is to have the servers automatically copy the process software to each client and then run the installation program for the process software at each client computer. The user executes the program that installs the process software on his client computer 212 then exits the process 108.

In step 104 a determination is made whether the process software is to be deployed by sending the process software to users via e-mail. The set of users where the process software will be deployed are identified together with the addresses of the user client computers 105. The process software is sent via e-mail 204 to each of the users' client computers. The users then receive the e-mail 205 and then detach the process software from the e-mail to a directory on their client computers 206. The user executes the program that installs the process software on his client computer 212 then exits the process 108.

Lastly, a determination is made on whether to the process software will be sent directly to user directories on their client computers 106. If so, the user directories are identified 107. The process software is transferred directly to the user's client computer directory 207. This can be done in several ways such as but not limited to sharing of the file system directories and then copying from the sender's file system to the recipient user's file system or alternatively using a transfer protocol such as File Transfer Protocol (FTP). The users access the directories on their client file systems in preparation for installing the process software 208. The user executes the program that installs the process software on his client computer 212 then exits the process 108.

The process software is integrated into a client, server and network environment by providing for the process software to coexist with applications, operating systems and network operating systems software and then installing the process software on the clients and servers in the environment where the process software will function.

The first step is to identify any software on the clients and servers including the network operating system where the process software will be deployed that are required by the process software or that work in conjunction with the process software. This includes the network operating system that is software that enhances a basic operating system by adding networking features.

Next, the software applications and version numbers will be identified and compared to the list of software applications and version numbers that have been tested to work with the process software. Those software applications that are missing or that do not match the correct version will be upgraded with the correct version numbers. Program instructions that pass parameters from the process software to the software applications will be checked to ensure the parameter lists matches the parameter lists required by the process software. Conversely parameters passed by the software applications to the process software will be checked to ensure the parameters match the parameters required by the process software. The client and server operating systems including the network operating systems will be identified and compared to the list of operating systems, version numbers and network software that have been tested to work with the process software. Those operating systems, version numbers and network software that do not match the list of tested operating systems and version numbers will be upgraded on the clients and servers to the required level.

After ensuring that the software, where the process software is to be deployed, is at the correct version level that has been tested to work with the process software, the integration is completed by installing the process software on the clients and servers.

In FIG. 10, Step 220 begins the integration of the process software. The first thing is to determine if there are any process software programs that will execute on a server or servers 221. If this is not the case, then integration proceeds to 227. If this is the case, then the server addresses are identified 222. The servers are checked to see if they contain software that includes the operating system (OS), applications, and network operating systems (NOS), together with their version numbers that have been tested with the process software 223. The servers are also checked to determine if there is any missing software that is required by the process software 223.

A determination is made if the version numbers match the version numbers of OS, applications and NOS that have been tested with the process software 224. If all of the versions match and there is no missing required software the integration continues in 227.

If one or more of the version numbers do not match, then the unmatched versions are updated on the server or servers with the correct versions 225. Additionally if there is missing required software, then it is updated on the server or servers 225. The server integration is completed by installing the process software 226.

Step 227 which follows either 221, 224 or 226 determines if there are any programs of the process software that will execute on the clients. If no process software programs execute on the clients the integration proceeds to 230 and exits. If this not the case, then the client addresses are identified 228.

The clients are checked to see if they contain software that includes the operating system (OS), applications, and network operating systems (NOS), together with their version numbers, that have been tested with the process software 229. The clients are also checked to determine if there is any missing software that is required by the process software 229.

A determination is made as to whether the version numbers match the version numbers of OS, applications and NOS that have been tested with the process software 231. If all of the versions match and there is no missing required software, then the integration proceeds to 230 and exits.

If one or more of the version numbers do not match, then the unmatched versions are updated on the clients with the correct versions 232. In addition, if there is missing required software then it is updated on the clients 232. The client integration is completed by installing the process software on the clients 233. The integration proceeds to 230 and exits.

The process software can be stored on a shared file system accessible from one or more servers. The process software is executed via transactions that contain data and server processing requests that use CPU units on the accessed server. CPU units are units of time such as minutes, seconds, hours on the central processor of the server. Additionally the assessed server may make requests of other servers that require CPU units. CPU units are an example that represents but one measurement of use. Other measurements of use include but are not limited to network bandwidth, memory usage, storage usage, packet transfers, complete transactions etc. When multiple customers use the same process software application, their transactions are differentiated by the parameters included in the transactions that identify the unique customer and the type of service for that customer. All of the CPU units and other measurements of use that are used for the services for each customer are recorded. When the number of transactions to any one server reaches a number that begins to affect the performance of that server, other servers are accessed to increase the capacity and to share the workload Likewise when other measurements of use such as network bandwidth, memory usage, storage usage, etc. approach a capacity so as to affect performance, additional network bandwidth, memory usage, storage etc. are added to share the workload. The measurements of use used for each service and customer are sent to a collecting server that sums the measurements of use for each customer for each service that was processed anywhere in the network of servers that provide the shared execution of the process software. The summed measurements of use units are periodically multiplied by unit costs and the resulting total process software application service costs are alternatively sent to the customer and or indicated on a web site accessed by the customer which then remits payment to the service provider. In another embodiment, the service provider requests payment directly from a customer account at a banking or financial institution.

In another embodiment, if the service provider is also a customer of the customer that uses the process software application, the payment owed to the service provider is reconciled to the payment owed by the service provider to minimize the transfer of payments.

The process software is shared, simultaneously serving multiple customers in a flexible, automated fashion. It is standardized, requiring little customization and it is scalable, providing capacity on demand in a pay-as-you-go model.

The process software can be stored on a shared file system accessible from one or more servers. The process software is executed via transactions that contain data and server processing requests that use CPU units on the accessed server. CPU units are units of time such as minutes, seconds, hours on the central processor of the server. Additionally the assessed server may make requests of other servers that require CPU units. CPU units are an example that represents but one measurement of use. Other measurements of use include but are not limited to network bandwidth, memory usage, storage usage, packet transfers, complete transactions etc.

When multiple customers use the same process software application, their transactions are differentiated by the parameters included in the transactions that identify the unique customer and the type of service for that customer. All of the CPU units and other measurements of use that are used for the services for each customer are recorded. When the number of transactions to any one server reaches a number that begins to affect the performance of that server, other servers are accessed to increase the capacity and to share the workload. Likewise, when other measurements of use such as network bandwidth, memory usage, storage usage, etc. approach a capacity so as to affect performance, additional network bandwidth, memory usage, storage etc. are added to share the workload.

The measurements of use used for each service and customer are sent to a collecting server that sums the measurements of use for each customer for each service that was processed anywhere in the network of servers that provide the shared execution of the process software. The summed measurements of use units are periodically multiplied by unit costs and the resulting total process software application service costs are alternatively sent to the customer and or indicated on a web site accessed by the customer which then remits payment to the service provider.

In another embodiment, the service provider requests payment directly from a customer account at a banking or financial institution.

In another embodiment, if the service provider is also a customer of the customer that uses the process software application, the payment owed to the service provider is reconciled to the payment owed by the service provider to minimize the transfer of payments.

In FIG. 11, Step 240 begins the On Demand process. A transaction is created than contains the unique customer identification, the requested service type and any service parameters that further specify the type of service 241. The transaction is then sent to the main server 242. In an On Demand environment the main server can initially be the only server, then as capacity is consumed other servers are added to the On Demand environment.

The server central processing unit (CPU) capacities in the On Demand environment are queried 243. The CPU requirement of the transaction is estimated, then the servers available CPU capacity in the On Demand environment are compared to the transaction CPU requirement to see if there is sufficient CPU available capacity in any server to process the transaction 244. If there is not sufficient server CPU available capacity, then additional server CPU capacity is allocated to process the transaction 248. If there was already sufficient Available CPU capacity then the transaction is sent to a selected server 245.

Before executing the transaction, a check is made of the remaining On Demand environment to determine if the environment has sufficient available capacity for processing the transaction. This environment capacity consists of such things as but not limited to network bandwidth, processor memory, storage etc. 246. If there is not sufficient available capacity, then capacity will be added to the On Demand environment 247. Next the required software to process the transaction is accessed, loaded into memory, then the transaction is executed 249.

The usage measurements are recorded 250. The usage measurements consists of the portions of those functions in the On Demand environment that are used to process the transaction. The usage of such functions as, but not limited to, network bandwidth, processor memory, storage and CPU cycles are what is recorded. The usage measurements are summed, multiplied by unit costs and then recorded as a charge to the requesting customer 251. If the customer has requested that the On Demand costs be posted to a web site 252 then they are posted 253.

If the customer has requested that the On Demand costs be sent via e-mail to a customer address 254 then they are sent 255. If the customer has requested that the On Demand costs be paid directly from a customer account 256 then payment is received directly from the customer account 257. The last step is to exit the On Demand process 258.

The process software may be deployed, accessed and executed through the use of a virtual private network (VPN), which is any combination of technologies that can be used to secure a connection through an otherwise unsecured or untrusted network. The use of VPNs is to improve security and for reduced operational costs. The VPN makes use of a public network, usually the Internet, to connect remote sites or users together. Instead of using a dedicated, real-world connection such as leased line, the VPN uses “virtual” connections routed through the Internet from the company's private network to the remote site or employee.

The process software may be deployed, accessed and executed through either a remote-access or a site-to-site VPN. When using the remote-access VPNs the process software is deployed, accessed and executed via the secure, encrypted connections between a company's private network and remote users through a third-party service provider. The enterprise service provider (ESP) sets a network access server (NAS) and provides the remote users with desktop client software for their computers. The telecommuters can then dial a toll-free number or attach directly via a cable or DSL modem to reach the NAS and use their VPN client software to access the corporate network and to access, download and execute the process software.

When using the site-to-site VPN, the process software is deployed, accessed and executed through the use of dedicated equipment and large-scale encryption that are used to connect a companies multiple fixed sites over a public network such as the Internet.

The process software is transported over the VPN via tunneling which is the process of placing an entire packet within another packet and sending it over a network. The protocol of the outer packet is understood by the network and both points, called tunnel interfaces, where the packet enters and exits the network.

In FIGS. 12 and 13, Step 260 begins the Virtual Private Network (VPN) process. A determination is made to see if a VPN for remote access is required 261. If it is not required, then proceed to 262. If it is required, then determine if the remote access VPN exists 264.

If it does exist, then proceed to 265. Otherwise identify the third party provider that will provide the secure, encrypted connections between the company's private network and the company's remote users 276. The company's remote users are identified 277. The third party provider then sets up a network access server (NAS) 278 that allows the remote users to dial a toll free number or attach directly via a cable or DSL modem to access, download and install the desktop client software for the remote-access VPN 279.

After the remote access VPN has been built or if it been previously installed, the remote users can then access the process software by dialing into the NAS or attaching directly via a cable or DSL modem into the NAS 265. This allows entry into the corporate network where the process software is accessed 266. The process software is transported to the remote user's desktop over the network via tunneling. That is the process software is divided into packets and each packet including the data and protocol is placed within another packet 267. When the process software arrives at the remote user's desktop, it is removed from the packets, reconstituted and then is executed on the remote users desktop 268.

A determination is made to see if a VPN for site to site access is required 262. If it is not required, then proceed to exit the process 263. Otherwise, determine if the site to site VPN exists 269. If it does exist, then proceed to 272. Otherwise, install the dedicated equipment required to establish a site to site VPN 270. Then build the large scale encryption into the VPN 271.

After the site to site VPN has been built or if it had been previously established, the users access the process software via the VPN 272. The process software is transported to the site users over the network via tunneling 273. That is the process software is divided into packets and each packet including the data and protocol is placed within another packet 274. When the process software arrives at the remote user's desktop, it is removed from the packets, reconstituted and is executed on the site users desktop 275. Proceed to exit the process 263.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein. 

What is claimed is:
 1. A method comprising: inputting average power consumption goals and timing delay goals for an integrated circuit chip design into a computerized device; identifying a plurality of valid temperature and voltage combinations that allow integrated circuit chips produced according to said integrated circuit chip design to operate within said average power consumption goals and said timing delay goals, using said computerized device; selecting temperature cut points from said valid temperature and voltage combinations for each of said integrated circuit chips using said computerized device; calculating a power consumption amount of each of said temperature cut points using said computerized device, adjusting said temperature cut points based on said calculating of said power consumption amount until said temperature cut points achieve said average power consumption goals; testing each of said integrated circuit chips using testing equipment operatively connected to said computerized device; and recording in memory of said integrated circuit chips said temperature cut points.
 2. The method according to claim 1, further comprising: sorting said integrated circuit chips into voltage bins based on a timing delay of said integrated circuit chips; and determining a percentage of said integrated circuit chips sorted into each of said voltage bins, using said computerized device.
 3. The method according to claim 2, further comprising determining an amount of time each of said integrated circuit chip will be operating within each different temperature range defined by said temperature cut points, using said computerized device.
 4. The method according to claim 3, further comprising calculating an average system power, using said computerized device, based on: said percentage of said integrated circuit chips sorted into each of said voltage bins; said amount of time each of said integrated circuit chip will be operating within each different temperature range defined by said temperature cut points; and said power consumption amount of each of said temperature cut points of each of said voltage bins.
 5. The method according to claim 1, each of said integrated circuit chips altering a current operating voltage based on a current operating temperature and said temperature cut points in said memory during in-service operations.
 6. The method according to claim 1, a total power consumption of each of said integrated circuit chips comprises a sum of dynamic power consumption and static power consumption.
 7. A method comprising: inputting average power consumption goals and timing delay goals for an integrated circuit chip design into a computerized device; identifying a plurality of valid temperature and voltage combinations that allow integrated circuit chips produced according to said integrated circuit chip design to operate within said average power consumption goals and said timing delay goals, using said computerized device; selecting voltage bins for said integrated circuit chips, each of said integrated circuit chips being assigned to one of said voltage bins based on a timing delay of said integrated circuit chips; selecting temperature cut points from said valid temperature and voltage combinations for each of said voltage bins using said computerized device; calculating, for each of said temperature cut points of each of said voltage bins, a power consumption amount using said computerized device; adjusting said temperature cut points based on said calculating of said power consumption amount until said temperature cut points achieve said average power consumption goals; testing each of said integrated circuit chips using testing equipment operatively connected to said computerized device, sorting said integrated circuit chips into said voltage bins based on said testing; and recording in memory of said integrated circuit chips said temperature cut points corresponding to a voltage bin of said voltage bins into which each of said integrated circuit chips has been sorted.
 8. The method according to claim 7, further comprising determining a percentage of said integrated circuit chips sorted into each of said voltage bins, using said computerized device.
 9. The method according to claim 8, further comprising determining an amount of time each of said integrated circuit chip will be operating within each different temperature range defined by said temperature cut points, using said computerized device.
 10. The method according to claim 9, further comprising calculating an average system power, using said computerized device, based on: said percentage of said integrated circuit chips sorted into each of said voltage bins; said amount of time each of said integrated circuit chip will be operating within each different temperature range defined by said temperature cut points; and said power consumption amount of each of said temperature cut points of each of said voltage bins.
 11. The method according to claim 7, each of said integrated circuit chips altering a current operating voltage based on a current operating temperature and said temperature cut points in said memory during in-service operations.
 12. The method according to claim 7, a total power consumption of each of said integrated circuit chips comprises a sum of dynamic power consumption and static power consumption.
 13. A method comprising: inputting average power consumption goals and timing delay goals for an integrated circuit chip design into a computerized device, said integrated circuit chips produced according to said integrated circuit chip design having temperature inversion performance characterized by decreasing timing delay as operating temperature increases; automatically identifying a plurality of valid temperature and voltage combinations that allow said integrated circuit chips to operate within said average power consumption goals and said timing delay goals, using said computerized device; selecting voltage bins for said integrated circuit chips, each of said integrated circuit chips being assigned to one of said voltage bins based on a timing delay of said integrated circuit chips; automatically selecting temperature cut points from said valid temperature and voltage combinations for each of said voltage bins using said computerized device, said temperature cut points directing each integrated circuit chip to operate at a corresponding operating voltage of said operating voltages when said integrated circuit chip has a temperature within a corresponding temperature range defined by said temperature cut points; automatically calculating, for each of said temperature cut points of each of said voltage bins, a power consumption amount based on said valid temperature and voltage combinations of each of said temperature cut points within each of said voltage bins, using said computerized device; adjusting said temperature cut points based on said calculating of said power consumption amount until said temperature cut points achieve said average power consumption goals; testing each of said integrated circuit chips using testing equipment operatively connected to said computerized device to determine selective voltage bin test results of each of said integrated circuit chips; sorting said integrated circuit chips into said voltage bins based on said selective voltage bin test results; and automatically recording in memory of said integrated circuit chips said temperature cut points corresponding to a voltage bin of said voltage bins into which each of said integrated circuit chips has been sorted.
 14. The method according to claim 13, further comprising determining a percentage of said integrated circuit chips sorted into each of said voltage bins, using said computerized device.
 15. The method according to claim 14, further comprising determining an amount of time each of said integrated circuit chip will be operating within each different temperature range defined by said temperature cut points, using said computerized device.
 16. The method according to claim 15, further comprising calculating an average system power, using said computerized device, based on: said percentage of said integrated circuit chips sorted into each of said voltage bins; said amount of time each of said integrated circuit chip will be operating within each different temperature range defined by said temperature cut points; and said power consumption amount of each of said temperature cut points of each of said voltage bins.
 17. The method according to claim 13, each of said integrated circuit chips altering a current operating voltage based on a current operating temperature and said temperature cut points in said memory during in-service operations.
 18. The method according to claim 13, a total power consumption of each of said integrated circuit chips comprises a sum of dynamic power consumption and static power consumption.
 19. A computer program product comprising a computer readable storage medium having program code embodied therewith, the program code being readable/executable by a computer to perform a method comprising: inputting average power consumption goals and timing delay goals for an integrated circuit chip design into a computerized device; identifying a plurality of valid temperature and voltage combinations that allow integrated circuit chips produced according to said integrated circuit chip design to operate within said average power consumption goals and said timing delay goals, using said computerized device; selecting temperature cut points from said valid temperature and voltage combinations for each of said integrated circuit chips using said computerized device; calculating a power consumption amount of each of said temperature cut points using said computerized device; adjusting said temperature cut points based on said calculating of said power consumption amount until said temperature cut points achieve said average power consumption goals; testing each of said integrated circuit chips using testing equipment operatively connected to said computerized device; and automatically recording in memory of said integrated circuit chips said temperature cut points.
 20. The computer program product according to claim 19, said method further comprising: sorting said integrated circuit chips into voltage bins based on a timing delay of said integrated circuit chips; and determining a percentage of said integrated circuit chips sorted into each of said voltage bins, using said computerized device.
 21. The computer program product according to claim 20, further comprising determining an amount of time each of said integrated circuit chip will be operating within each different temperature range defined by said temperature cut points, using said computerized device.
 22. The computer program product according to claim 21, further comprising calculating an average system power, using said computerized device, based on: said percentage of said integrated circuit chips sorted into each of said voltage bins; said amount of time each of said integrated circuit chip will be operating within each different temperature range defined by said temperature cut points; and said power consumption amount of each of said temperature cut points of each of said voltage bins.
 23. The computer program product according to claim 19, each of said integrated circuit chips altering a current operating voltage based on a current operating temperature and said temperature cut points in said memory during in-service operations.
 24. The computer program product according to claim 19, a total power consumption of each of said integrated circuit chips comprises a sum of dynamic power consumption and static power consumption. 